1. Field of the Invention
The present invention relates to a method and apparatus for carrying out circuit simulation which simulates, at high speed, a circuit that is an object of circuit simulation.
In particular, the present invention relates to a circuit simulation technique for simulating and inspecting a MOS large-scale integrated (abbreviated to LSI) circuit, which includes a plurality of MOS semiconductor devices, as an object of circuit simulation, and for thus checking if the MOS LSI circuit satisfies design specifications or for improving the performance of the MOS LSI circuit.
2. Description of the Related Art
For simulating a circuit to be simulated using a circuit simulator or the like, a current flowing into each terminal in the circuit or a voltage at the terminal are calculated on the basis of the connectional relationship of each modeled circuit element in the circuit, the characteristics of the modeled circuit element, and the connectional relationship of an input terminal of the circuit to be simulated. In this case, when the circuit to be simulated is handled as it is and simulated, it takes too much time for the simulation. It is hard to achieve circuit simulation efficiently in a short period of time. In particular, a MOS LSI circuit is large in scale. In the circumstances, it is required that the circuit to be simulated is simplified while the accuracy in operation of the circuit is ensured, and thus the time required for simulation is shortened in order to carry out simulation at high speed.
For a better understanding of the problem lying in a circuit simulation method in accordance with a related art, the circuit simulation method and a circuit to be simulated will be described with reference to FIGS. 1A, 1B and 2 that will be referred to in “Brief Description of the Drawings.”
FIGS. 1A and 1B are flowcharts each describing an example of a circuit simulation method in accordance with the related art; and FIG. 2 is a circuit diagram showing a typical example of a circuit to be simulated which will be compressed according to the circuit simulation method described in FIGS. 1A and 1B.
For brevity's sake, a signal delay circuit composed of two n-type MOS (NMOS) transistors as shown in a portion (A) of FIG. 2, and a logic circuit composed of three NMOS transistors as shown in a portion (C) of FIG. 2 will be discussed as the circuit to be simulated. A circuit including one NMOS transistor as shown in a portion (B) of FIG. 2 is, as described later, a compressed form of the signal delay circuit shown in the portion (A) of FIG. 2.
The circuit simulation method shown in FIGS. 1A, 1B and 2 has been disclosed in, for example, the specification of a patent application of the related art (Japanese Patent Application No. 8-198074 filed on Jul. 26, 1996) filed by the same inventor and applicant as those of this application.
In the flowchart of FIG. 1A, first, a net Ni (i is a positive integer) (In the portions (A) and (B) of FIG. 2, i is any one of 1 to 3, and in the portion (C) thereof, i is any one of 10, 20, 30, and 40) within a circuit to be simulated, for example, a net N1 in the portion (A) of FIG. 2 is selected (step S200). An identification number marking a net concerned is assigned to the net Ni, for example, net N1. That is to say, an identification number a1 is assigned to the net N1 (step S210).
At step S220 shown in FIG. 1A, circuit elements interconnected within the net Ni and exhibiting the same characteristics (identical circuit elements) are inspected. What is referred to as identical circuit elements are circuit elements exhibiting the same characteristics such as NMOS transistors or p-type MOS (PMOS) transistors that are active circuit elements to be operated with power supplied from a source power supply VSS and drain power supply VDD, capacitors that are passive circuit elements, resistors, and diodes. That is to say, the identical circuit elements are circuit elements exhibiting mutually equivalent operational characteristics. For example, an NMOS transistor Q1 and NMOS transistor Q2 shown in the portion (A) of FIG. 2 are regarded as identical circuit elements.
If a plurality of identical circuit elements are detected at step S230, control is passed to step S240. Otherwise, control is passed to step S290. At step S240, the same identification number is assigned to the identical circuit elements detected at step S220. For example, an identification number b1 is assigned to both the NMOS transistor Q1 and NMOS transistor Q2 (step S240).
As shown in FIG. 1B, it is checked if corresponding terminals of the thus detected identical circuit elements exhibit the same characteristics (step S245). For example, in the portion (A) of FIG. 2, it is checked if the electrical conditions for connection of the source, drain, and bulk resistor of the NMOS transistor Q1 are the same as those of the source, drain, and bulk resistor of the NMOS transistor Q2 (step 250).
Further, in FIG. 1B, if the thus inspected corresponding terminals exhibit the same characteristics, control is passed to step S260. Otherwise, control is passed to step S280.
At step S260 shown in FIG. 1B, m (m is a positive integer equal to or larger than 2) circuit elements and terminals thereof exhibiting the same characteristics are integrated into one circuit element and terminals thereof. For example, the circuit elements shown in the portion (A) of FIG. 2 are integrated into the circuit element shown in the portion (B) thereof. Converting a circuit composed of a plurality of circuit elements and a plurality of terminals into a circuit having one simple circuit element and terminals is referred to as circuit compression.
For compressing the circuit shown in the portion (A) of FIG. 2 into the circuit shown in the portion (B) thereof, the characteristics of an NMOS transistor Q1′ must be determined so that a current flowing through the terminals of the NMOS transistor Q1′ (refer to the portion (B) of FIG. 2) will be twice as large as a current flowing through the terminals of the NMOS transistor Q1 that has not been integrated (refer to the portion (A) of FIG. 2). In other words, the parameters of the circuit element are determined so that the gate capacitance and drain current of the NMOS transistor Q1′ will be twice as large as those of the NMOS transistor Q1.
As a result of inspecting terminals to which the same identification number has been assigned, if it is recognized at step S280 that the terminals are not identical to each other, the identification number is released (for example, the identification number b1 assigned to the NMOS transistors Q1 and Q2 shown in the portion (A) of FIG. 2 is released). The control flow is then returned to step S220. Regarding circuit elements and terminals having identification numbers assigned thereto, circuit elements and terminals having the same identification number can be judged to exhibit the same characteristics. Repetition of a sequence for judging if circuit elements exhibit the same characteristics can be avoided.
Regarding an NMOS transistor Q10 and NMOS transistor Q20 in the logic circuit shown in the portion (C) of FIG. 2 which have been judged as identical circuit elements according to the same procedure adopted to inspect the circuit elements shown in the portion (A) of FIG. 2 and to which the same identification number b10 has been assigned, the drains thereof are connected to the nets N20, and the bulk resistors thereof are connected to the nets N30. However, the source of the NMOS transistor Q10 is connected to the net N30, while the source of the NMOS transistor Q20 is connected to the net N40. The sources of the NMOS transistor Q10 and NMOS transistor Q20 must be inspected in order to check if they exhibit the same characteristics, even though the same identification number t1 has already been assigned to the sources.
For inspecting the sources of the NMOS transistor Q10 and NMOS transistor Q20 to check if they exhibit the same characteristics, the circuit elements connected to the sources that are corresponding terminals are inspected in order to check if they exhibit the same characteristics. In the case of the portion (C) of FIG. 2, the source of the NMOS transistor Q10 is connected to a source power supply VSS, while the source of the NMOS transistor Q20 is connected to the drain of the NMOS transistor Q30. It is therefore judged that the source of the NMOS transistor Q10 and the source of the NMOS transistor Q20 do not exhibit the same characteristics. In this case, the same identification number t1 assigned to the sources is released at step S280.
According to the circuit simulation method of the related art described in conjunction with FIGS. 1A, 1B and 2, circuit simulation is carried out by compressing a circuit that includes circuit elements that have been verified to exhibit the same characteristics as a result of inspecting the circuit elements to check if they exhibit the same characteristics (that is, if the operational characteristics thereof are equivalent to each other) on the basis of the connectional relationship of an input terminal of the circuit to be simulated, the configuration of the circuit to be simulated, and the operational characteristics of the plurality of corresponding circuit elements.
However, according to the circuit simulation method of the related art, as described in conjunction with FIGS. 1A, 1B and 2, when the operations of a circuit to be simulated such as a MOS LSI circuit are inspected, a plurality of circuit elements that have been judged to exhibit the same characteristics are finally inspected for equivalence in operational characteristics merely by inspecting circuit elements connected to corresponding terminals of the plurality of circuit elements to see if they exhibit the same characteristics.
As mentioned above, according to the circuit simulation method of the related art, only circuit elements located in a limited area within a circuit can be inspected in order to see if they exhibit the same characteristics. It is difficult to distinguish all circuit elements exhibiting equivalent operational characteristics in a circuit to be simulated. The circuit is therefore not compressed effectively.
The total number of circuit elements increases with an increase in scale of a circuit to be simulated. The time required for simulation therefore increases. This causes the problem in that it is hard to achieve circuit simulation at high speed.